Many integrated circuit devices (e.g., memory devices) operate in-sync with externally supplied clock signals by generating one or more internal clock signals that are preferably phase locked with the external clock signal and with each other. As will be understood by those skilled in the art, accurate phase locking of clock signals can be especially important for integrated circuit devices that operate a high frequencies. Such integrated circuit devices may include merged memory with logic (MML) devices, Rambus DRAM devices and double data rate synchronous DRAM devices (DDR-SDRAM).
Conventional techniques for providing clock signals across a relatively large integrated circuit chip typically suffer from an inability to accurately match clock signal phase, since clock signals traversing different length signal paths experience different signal delays (e.g., RC delays). These nonuniform delays make it difficult to accurate maintain synchronization of all devices on an integrated circuit chip. To address these limitations, many delay locked loop (DLL) integrated circuits generate advanced clock signals to compensate for the delays associated with signal path traversal. For example, FIG. 1 illustrates a conventional delay locked loop integrated circuit 10 that generates an advanced clock signal ADCLKD. This delay locked loop integrated circuit 10 includes a phase detector 12, a charge pump 14, a variable delay circuit 16 and a delay compensation circuit 18. The phase detector 12 receives a reference clock signal RCLK and a feedback clock signal (output on signal line 21 by the delay compensation circuit 18) and generates a pair of phase detected signals on signal lines 13a and 13b. These phase detected signals are provided to the charge pump 14 which generates a phase control signal (VCON1). This phase control signal VCON1 may have a magnitude that is proportional to a phase difference between the reference clock signal RCLK and the feedback clock signal.
The variable delay circuit 16 generates the advanced clock signal ADCLKD as a delayed version of the reference clock signal RCLK. As illustrated by FIG. 2, which is a block diagram of the variable delay circuit 16 of FIG. 1, the degree to which the advanced clock signal ADCLKD is delayed in time or phase relative to the reference clock signal RCLK is a function of the number of delay stages ST1-STn and the delay provided by each stage. As will be understood by those skilled in the art, the delay provided by each stage may be a function of the magnitude of the phase control voltage VCON1.
Unfortunately, the degree to which the delay provided by the variable delay circuit 16 of FIGS. 1-2 can be varied is limited by the fixed number of delay stages and the limited degree to which the delay of each stage can be varied in response to variations in the magnitude of the phase control signal VCON1. Such limited delay variation can increase the likelihood that the phase locked loop will experience jitter when high frequency and low frequency reference clock signals RCLK are used. Moreover, limited delay variation may make it difficult to control the timing and phase of such advanced clock signals to exactly match the delays associated with signal path traversal.
Thus, notwithstanding the delay locked loop integrated circuit of FIGS. 1-2, there continues to be a need for improved phase locked loop integrated circuits having greater signal frequency bandwidth and other improved characteristics.